The present invention relates to an apparatus and method for the communication of digital signals at high speed, and more particularly the communication of modulated digital signals.
The communication of digital information within a computer system can represent one of the bottlenecks in achieving high rates of computation. It is becoming apparent to many that conventional technologies for moving data between semiconductor memory and a Central Processor Unit (CPU), while much faster than moving data between other types of storage devices, such as CD-ROMs or magnetic disks, and the CPU, are approaching a practical upper limit. One solution that has been applied to try to solve this problem of communication speed is to increase the system clock rate. However, given the pinout geometries of conventional memory systems, it is difficult to operate such systems at speeds above about 100 MHz. Another approach that could be taken is to attempt to clock data at both the rising edge and the falling edge of clock signals. This approach places severe constraints on clock access times, requiring at least a factor of two improvement in output delay of the memory chip. Another approach involves the use of a wider bus, employing 128 bits rather than 64 bits of width. Such an approach involves many changes in computer system design, including a major redesign of PCB board layouts, changes in pinouts and significant increases of pin counts for packages, and changes in the length of words in software design, for example.
Yet another approach is the Direct Rambus DRAM technology. In this approach, a wide internal bus is connected via a high-speed interface to a narrow external bus. The internal bus 144/128-bit data path operates at 16 bytes every 10 ns internally, which is transformed into an external 2-byte wide 1.25 ns bus. The system uses a bus clock at 400 MHz. Because data transfers are synchronized to both clock edges, the rate is effectively raised to 800 MHz. This system is stated to yield a 1,600 Mbyte/s bandwidth. One significant electrical difference from conventional systems is that memory modules are connected such that any data signal must sequentially traverse all the memory modules present, rather than reaching a particular module without passing all of the others.
Conventional processor to memory interconnection buses drive a set of memory components, typically SIMMs or DIMMs, with a motherboard signal trace which runs between SIMM connectors (FIG. 1). Typically, this line is driven with a series resistance, and treated as a single lumped capacitive load. Signals are driven with a single polarity, rail to rail, as baseband digital signals.
The impedance of such a bus wire is very low, because of the periodic capacitive stubs added by the connector and SIMM traces and components. An initially unloaded 100 ohm impedance line, constructed as a stripline on commercial FR-4 material having K=4, has a capacitance per unit length of 0.67 pF/cm. When loaded with a relatively modest 20 pF load each 2 cm, the effective capacitance per unit length rises to 10.67 pF/cm, resulting in an impedance of about 25 ohms, and a reduction in the speed of propagation from half the speed of light (c/2) to approximately one-eighth the speed of light (c/8). This dramatic speed and impedance reduction makes it impractical, from a noise and power standpoint, to correctly terminate the bus with a parallel termination. Series terminations cannot be used for high quality signals because of the signal stairstep behavior at intermediate positions in a multidrop environment.
Moreover, the equivalent electrical line length of the 2 cm connector spacing rises to 16 cm, with approximately 500 ps of delay. This delay is significant compared to the risetime of a typical digital signal. The delay encourages stub reflections in a correctly terminated environment. Most such buses are driven with a series resistance to intentionally slow the incident edges, resulting in poor bandwidth, and sloppy signaling.
Conventional high-speed digital systems suffer from a variety of problems. An article entitled xe2x80x9cControlling crosstalk in high-speed digital systems,xe2x80x9d which appeared in the May 1999 issue of Electronic Systems at page 31, makes reference to crosstalk in the following terms. xe2x80x9cThe advent of higher switching speeds in modern digital systems has introduced a host of difficult-to-solve problems: signal reflections, delay-time degradation, crosstalk, and electromagnetic-compatibility failures. At driver-IC switching times of 4 to 5 ns or less, PCB traces begin to exhibit their circuit characteristics. Unfortunately, these parameters are generally unwelcome and must be carefully designed around. Of all high-speed effects, crosstalk is perhaps the least understood and the hardest to predict. Yet, it can be controlled and even eliminated.xe2x80x9d
It is therefore a principal object of this invention to provide a high-speed digital distribution system that includes a transmission line bus that carries modulated digital signals and reference signals. It is another principal object for such a high speed digital distribution system to modulate digital data using quadrature amplitude modulation. It is another principal object for such a high speed digital distribution system to include a bus interface that is electrically connected to the bus and one or more digital component interfaces that are electromagnetically connected to the bus. It is another principal object for such a high speed digital distribution system to include one or more digital component interfaces that can be connected to or disconnected from the bus while the system is in operation.
A high-speed digital distribution system is presented which relates to a transmission line bus that carries modulated digital signals and reference signals. The transmission line bus has a first end electrically connected to a bus interface. The bus interface modulates digital data onto said transmission line bus and demodulates modulated digital data signals that it receives from the transmission line bus. The bus interface can transmit and receive a reference signal. At least one digital component interface is in electromagnetic communication with the transmission line bus. The digital component interface can also modulate digital data onto the transmission line bus and can demodulate modulated digital data signals received from the transmission line bus, and can transmit and receive a reference signal. The transmission line bus communicates modulated digital data in association with the reference signal between and among an external device connected to the bus interface and the at least one digital component interface. In another embodiment, the system includes a reference source which can provide a reference signal to at least one of the bus interface and the at least one digital component interface. In yet another embodiment, the system includes a digital component that is electrically interfaced with the at least one digital component interface, and that transmits and receives the digital data and the address signal. In still another embodiment, the digital data is quadrature amplitude modulated with the reference signal. In a further embodiment, the digital data is quadrature amplitude modulated with an encoding that uses one to five bits for the phase component and zero to three bits for the amplitude component. In yet a further embodiment the transmission line bus has characteristic impedance and has matched terminations at its first and second ends. In another embodiment, the reference signal and the modulated data signal can be multiplexed onto the same conductor of the transmission line bus. In another embodiment, the digital component interface includes a transmission line that can couple electromagnetic radiation to and from the transmission line bus. In another embodiment, the digital component interface includes a directional coupler that can communicate with the transmission line bus by coupling electromagnetic radiation to and from the transmission line bus. In another embodiment, the digital component interface is removably attached to the system. In yet another embodiment, the digital component interface can be attached to or removed from the system while the system is in operation. In still another embodiment, the digital component interface includes an electrical connection to a power supply.
The present invention further relates to an apparatus for distributing digital signals, which includes a transmission line bus having a first end. A first interface is electrically connected to the transmission line bus, and a second interface is electromagnetically coupled to the transmission line bus. A reference signal source that provides a reference signal including a phase component and an amplitude component is provided. A first digital device is electrically connected to the first interface and a second digital device is electrically connected to the second interface. One of the first interface and the second interface modulates digital data provided by the digital data device connected thereto with the reference signal to encode the digital data in a quadrature amplitude modulated signal and transmits the modulated data onto the transmission line bus, and another of the first interface and the second interface receives and demodulates the modulated digital data and provides demodulated data to the digital device connected thereto.
The present invention also relates to a method of distributing digital signals, which includes the steps of providing a reference signal, providing a transmission line bus, and providing a first interface and a second interface, at least one interface being electrically connected to the transmission line bus, and at least one interface being electromagnetically coupled to the transmission line bus, both interfaces adapted to receive and to transmit the reference signal. The method further includes the steps of providing digital data to the first interface, causing the first interface to modulate the digital data in conjunction with the reference signal and to impress the modulated data onto the transmission line bus in conjunction with the reference signal, and causing the second interface to receive and demodulate the modulated digital data in conjunction with the reference signal. In another embodiment, the method includes the step of causing the first interface to quadrature amplitude modulate the digital data with the reference signal and to impress the modulated data onto the transmission line bus in conjunction with the reference signal. In yet another embodiment, the method includes the step of causing the first interface to quadrature amplitude modulate the digital data with the reference signal in which the encoding uses from one to five bits for a phase component and from zero to three bits for and amplitude component. In still another embodiment, the data is frequency modulated. In a further embodiment, the data is spread spectrum modulated. In still a further embodiment, the data is amplitude modulated. In still a further embodiment, the data is single sideband modulated.
The present invention further relates to a high-speed digital distribution system which includes a transmission line bus which has a first end that carries modulated digital signals and reference signals, a bus interface electrically connected to the first end of the transmission line bus so that the bus interface can modulate digital data onto the transmission line bus and can demodulate modulated digital data signals received from the transmission line bus. The bus interface can transmit and receive a reference signal. The system also includes at least one digital component in electromagnetic communication with the transmission line bus so that the digital component can modulate digital data onto the transmission line bus and can demodulate modulated digital data signals received from the transmission line bus. The digital component can transmit and can receive a reference signal. The transmission line bus communicates modulated digital data in association with a reference signal between and among an external device connected to the bus interface and the at least one digital component. In another embodiment, the system includes a reference source which can provide a reference signal to at least one of the bus interface and the at least one digital component. In still another embodiment, a reference signal includes a phase component and an amplitude component. In still a further embodiment, a reference signal is quadrature amplitude modulated. In yet a further embodiment, the digital data is encoded using from one to five bits for the phase component and from zero to three bits for the amplitude component. In other embodiments, the digital data may be modulated using frequency modulation, spread spectrum modulation, amplitude modulation, or single sideband encoding. In a further embodiment, the system may include a characteristic impedance and may be terminated with matched terminations at its first end and at a second end. In a still further embodiment, the system includes a series impedance substantially equal to the characteristic impedance and connected between the bus interface, that represents a voltage source, and the first end of the bus, and a parallel impedance substantially equal to the characteristic impedance and connected between the second end of the bus and ground. In yet a further embodiment, the system includes a bus interface that represents a current source, a parallel impedance substantially equal to the characteristic impedance that is connected between the first end of the bus and ground, and a parallel impedance substantially equal to the characteristic impedance and connected between the second end of the bus and ground. In another embodiment, the digital component includes a directional coupler in electromagnetic communication with the transmission line bus. In still another embodiment, the digital component is removably attached to the system. In yet another embodiment, the digital component can be attached to or detached from the system while the system is in operation. In still a further embodiment, the digital component includes a connection to a power supply. In a still further embodiment, one interface that is electromagnetically coupled to the transmission line bus can modulate data in conjunction with a reference signal and impress the modulated data on the transmission line bus in conjunction with the reference signal, and a second interface that is electromagnetically coupled to the transmission line bus can receive modulated data in conjunction with a reference signal from the transmission line bus and can demodulate the modulated data in conjunction with the reference signal.